The present disclosure relates to non-volatile semiconductor memories, and more particularly, techniques of reducing variations in write speed when a plurality of non-volatile memory cells are simultaneously written to the same threshold level.
A non-volatile semiconductor memory, such as a flash memory etc., typically includes a memory cell array including a plurality of memory cells arranged in a matrix, where each memory cell includes a gate electrode connected to a word line, a drain connected to a bit line, a source connected to a source line, and a floating gate or a charge trapping layer.
For example, in a non-volatile semiconductor memory including a trapping layer, charge (electrons or holes) are injected into and trapped by discrete patches of a trapping layer (a SiN film or a transition region at an interface between a SiN film and a top SiO2 film) which are located in an insulating film (SiO2) between the channel region and gate electrode of a memory cell. The value of information (data) stored in the memory cell is determined to be “0” or “1” based on the threshold level of the memory cell. The injection of electrons is assumed to mean write operation. The principle of the write operation will be described hereinafter.
FIG. 9 shows a memory cell in a conventional non-volatile semiconductor memory. The memory cell includes a semiconductor substrate 600 made of P-type silicon, a P-type channel region 601 provided on the semiconductor substrate 600, a first impurity region 602 (e.g., a drain) made of an N-type semiconductor provided on the semiconductor substrate 600 on one side of the channel region 601, a second impurity region 603 (e.g., a source) made of an N-type semiconductor provided on the semiconductor substrate 600 on the other side of the channel region 601, a bottom insulating film 604 made of a silicon oxide film provided on the semiconductor substrate 600, a trapping layer 605 made of a silicon oxynitride film provided on the bottom insulating film 604, a top insulating film 606 made of a silicon oxide film provided on the trapping layer 605, and a gate electrode 607 made of N-type polysilicon provided on the top insulating film 606.
During write operation, a voltage of about 9 V is applied to the gate electrode 607, a voltage of about 5 V is applied to the first impurity region (drain) 602, a voltage of 0 V is applied to the second impurity region (source) 603, and a voltage of 0 V is applied to the semiconductor substrate 600. As a result, a portion of electrons traveling from the second impurity region 603 toward the first impurity region 602 become hot by a high electric field in the vicinity of the first impurity region 602, and are locally injected into the trapping layer 605 in the vicinity of the first impurity region 602, so that the threshold level of the memory cell is increased.
The write operation of the non-volatile semiconductor memory is typically performed on a group of memory cells basis, such as on a byte-by-byte basis, on a word-by-word basis, etc. The write voltage is simultaneously applied to memory cells in the group, whereby the write time is reduced.
In the non-volatile semiconductor memory including the trapping layer, if voltages applied to the first impurity region 602 and the second impurity region 603 of the memory cell are switched, i.e., a voltage of 0 V is applied to the first impurity region 602 and a voltage of about 5 V is applied to the second impurity region 603, whereby electrons are also locally injected into the trapping layer 605 in the vicinity of the second impurity region 603. As a result, the memory cell can store two bits of data.
In recent years, however, as the capacity of non-volatile semiconductor memories has increased, the area of the memory cell array has also increased, and therefore, the length of bit lines provided in the memory cell array has also increased. Therefore, in write operation, the drain voltage varies depending on the position of the memory cell in the memory cell array because of a voltage drop caused by the resistance of the bit line, resulting in variations in write speed.
In addition, in the non-volatile semiconductor memory which includes the trapping layer and can store two bits of data in each memory cell, it is known that the memory state of a first bit has an influence on the write speed of a second bit, leading to variations in write speed.
To address these problems, there is a conventional technique of reducing variations in write speed by changing the level of a bit line voltage supplied to a bit line in a memory cell array, depending on a write address, during write operation (see Japanese Patent Publication No. 2003-109389).
In the conventional technique, however, a plurality of memory cells are simultaneously written under write conditions (a drain voltage and a drain voltage supply period) which are common to the memory cells. Therefore, variations in write speed between the memory cells which are simultaneously written cannot be reduced, leading to a degradation in the reliability of the memory cells. Moreover, because the write time depends on a memory cell having a low write speed, the write time increases due to variations in write speed.